Final Assessment Exercise Assessment 10%. Problem Statement You have been tasked with designing a Pulse-width-Modulated (PWM) waveform generator. This is to consist of a synthesisable VHDL module to generate a waveform with the following specification: The output from the module is a repetitive waveform with a duty-cycle variable from 0/255 to 255/255 i.e. 0% to 100%. This is controlled by an 8-bit std_logic_vector input to the module. The waveform is generated from an input clock of 1kHz. The output waveform frequency is fixed at 1kHz/255. Note that this choice is intended to make the problem easier. Variable Duty-cycle 0-100% T Fixed Period The module is to have the VHDL name pwm_gen and ports exactly as shown in the following figure: width(7:0) pwm clock reset pwm_gen You may assume inputs are already synchronized to the clock. Final Assessment Exercise Assessment 10%. Problem Statement You have been tasked with designing a Pulse-width-Modulated (PWM) waveform generator. This is to consist of a synthesisable VHDL module to generate a waveform with the following specification: The output from the module is a repetitive waveform with a duty-cycle variable from 0/255 to 255/255 i.e. 0% to 100%. This is controlled by an 8-bit std_logic_vector input to the module. The waveform is generated from an input clock of 1kHz. The output waveform frequency is fixed at 1kHz/255. Note that this choice is intended to make the problem easier. Variable Duty-cycle 0-100% T Fixed Period The module is to have the VHDL name pwm_gen and ports exactly as shown in the following figure: width(7:0) pwm clock reset pwm_gen You may assume inputs are already synchronized to the clock