fix the following behavioral verilog code:- (the output should be as the inage attached)

CODE:-

module jk_ff(j,k,clk,pre,clr,q,qbar);

input j,k,clk,pre,clr;

output q,qbar;

always @( posedge clk );//or pre or clr);

begin

if (pre==0)

q

qbar

else if(clr==0)

q

qbar

end

case ({j,k})

2'b00 : q

2'b01 : q

2'b10 : q

2'b11: q

endcase

endmodule

module tb_jk;

reg jj,kk,clk0=0,pret,clrt;

wire qq,qqbar;

jk_ff jk0(j,k,clk,pre,clr,q,qbar);

always #5 clk0 = ~clk0;

initial

begin

#10 jj = 0; kk = 1;

#10$display("j = %b, k = %b",jj,kk,", ","Q = %b",qq,", ","Qbar = %b",qqbar);

#10 jj = 0; kk = 0;

#10$display("j = %b, k = %b",jj,kk,", ","Q = %b",qq,", ","Qbar = %b",qqbar);

#10 jj = 1; kk = 0;

#10$display("j = %b, k = %b",jj,kk,", ","Q = %b",qq,", ","Qbar = %b",qqbar);

#10 jj = 1; kk = 1;

#10$display("j = %b, k = %b",jj,kk,", ","Q = %b",qq,", ","Qbar = %b",qqbar);

#10 pret = 0;clrt = 1;

#10$display("pret = %b (Active low)",pret,", ","Q = %b",qq,", ","Qbar = %b",qqbar);

#10 clrt = 0;pret = 1;

#10$display("clre = %b (Active low)",clrt,", ","Q = %b",qq,", ","Qbar = %b",qqbar);

#10 $finish;

end

endmodule

$iverilog -o main *.v = $vvp main = 0, k = 1, Q = 0, Qbar = 1 0, k = 0, Q = 0, Qbar = 1 , = 1, k = 0, Q = 1, Qbar = 0 = 1, k = 1, O = e, Obar = 1 pret = 0 (Active low), Q = 1, Qbar = 0 clre = 0 (Active low), O Q = 0, Qbar = 1 DU... =