following i have the implementations for each one : the program for the sorter $is$ : module sorter

input logic $[7$:$0]$ A$,$

input logic $[7$:$0]$ B$,$

output logic $[7$:$0]$ max,

output logic $[7$:$0]$ min

$)$;

always$\_$comb begin

if $($A $>$ B$)$ begin

max $=$ A;

min $=$ B;

end else begin

max $=$ B;

min $=$ A;

end

end

endmodule

the program for odd$-$even merge sort $is$ :

module even$\_$odd$\_$merge$\_$sorter$($

input logic $[7$:$0]$ A$,$

input logic $[7$:$0]$ B$,$

input logic $[7$:$0]$ C$,$

input logic $[7$:$0]$ D$,$

output logic $[7$:$0]$ max,

output logic $[7$:$0]$ second$\_$max,

output logic $[7$:$0]$ second$\_$min,

output logic $[7$:$0]$ min

$)$;

logic $[7$:$0]$ sorter$\_1\_$max;

logic $[7$:$0]$ sorter$\_1\_$min;

logic $[7$:$0]$ sorter$\_2\_$max;

logic $[7$:$0]$ sorter$\_2\_$min;

logic $[7$:$0]$ sorter$\_3\_$min;

logic $[7$:$0]$ sorter$\_4\_$max;

sorter sorter$\_1($A$,$ B$,$ sorter$\_1\_$max, sorter$\_1\_$min$)$;

sorter sorter$\_2($C$,$ D$,$ sorter$\_2\_$max, sorter$\_2\_$min$)$;

sorter sorter$\_3($sorter$\_1\_$max, sorter$\_2\_$max, max, sorter$\_3\_$min$)$;

sorter sorter$\_4($sorter$\_1\_$min, sorter$\_2\_$min, sorter$\_4\_$max, min$)$;

sorter sorter$\_5($sorter$\_3\_$min, sorter$\_4\_$max, second$\_$max, second$\_$min$)$;

endmodule

the program for the circuit $3is$ : module even$\_$odd$\_$merge$\_$sorter$\_$wrapper$($

input logic clk$,$

input logic rst$,$

input logic $[7$:$0]$ A$,$

input logic $[7$:$0]$ B$,$

input logic $[7$:$0]$ C$,$

input logic $[7$:$0]$ D$,$

output logic $[7$:$0]$ max,

output logic $[7$:$0]$ second$\_$max,

output logic $[7$:$0]$ second$\_$min,

output logic $[7$:$0]$ min

$)$;

logic $[7$:$0]$ regA, regB, regC, regD;

logic $[7$:$0]$ reg$\_$max, reg$\_$second$\_$max, reg$\_$second$\_$min, reg$\_$min;

logic $[7$:$0]$ sorter$\_1\_$max;

logic $[7$:$0]$ sorter$\_1\_$min;

logic $[7$:$0]$ sorter$\_2\_$max;

logic $[7$:$0]$ sorter$\_2\_$min;

logic $[7$:$0]$ sorter$\_3\_$min;

logic $[7$:$0]$ sorter$\_4\_$max;

$//$ Register Input

always$\_$ff@$($posedge clk$)$ begin

if $($rst$)$ begin

regA b$0$;

regB b$0$;

regC b$0$;

regD b$0$;

end else begin

regA A;

regB B;

regC C;

regD D;

end

end

$//$ intsantiate even$\_$odd$\_$merge$\_$sorter circuit

even$\_$odd$\_$merge$\_$sorter sorter$\_0($regA$,$ regB, regC, regD, reg$\_$max, reg$\_$second$\_$max, reg$\_$second$\_$min, reg$\_$min$)$;

$//$ Register Output

always$\_$ff@$($posedge clk$)$ begin

if $($rst$)$ begin

max b$0$;

second$\_$max b$0$;

second$\_$min b$0$;

min b$0$;

end else begin

max reg$\_$max;

second$\_$max reg$\_$second$\_$max;

second$\_$min reg$\_$second$\_$min;

min reg$\_$min;

end

end

endmodule

the program for techbench $is$ :

$so$ according $to$ all above programs i want a program for the circuit $4$ for vivado. thank you very much module even$\_$odd$\_$merge$\_$sorter$\_$tb;

parameter MEM$\_$SIZE $=30$;

logic clk$,$ rst;

logic $[7$:$0]$ A;

logic $[7$:$0]$ B;

logic $[7$:$0]$ C;

logic $[7$:$0]$ D;

logic $[7$:$0]$ max;

logic $[7$:$0]$ second$\_$max;

logic $[7$:$0]$ second$\_$min;

logic $[7$:$0]$ min;

logic $[63$:$0]$ test$\_$memory$[0$:MEM$\_$SIZE$-1]$;

integer i;

always begin

clk ;

#$5$ns;

clk ;

#$5$ns;

end

even$\_$odd$\_$merge$\_$sorter$\_$wrapper sorter$\_0($clk$,$ rst$,$ A$,$ B$,$ C$,$ D$,$ max, second$\_$max, second$\_$min, min$)$;

initial begin

$monitor$($$time, $"$ max$=\%$h$,$ second$\_$max$=\%$h$,$ second$\_$min$=\%$h$,$ min$=\%$h$",$ max, second$\_$max, second$\_$min, min$)$;

$display$("$Loading test vectors"$)$;

$readmemh$("$test$.$tv$",$ test$\_$memory$)$;

rst ;

repeat$(2)$ @$($posedge clk$)$;

rst ;

for $($i$=0$; i

so according to all above programs i want a program for the circuit $4$ for vivado. thank you very much