. For one type of TTL NAND gate the manufacturer specifies a minimum propagation delay of 5 ns and a maximum delay of 30 ns. a) Sketch the gate outputs for the following circuit when the x input changes from 1 to 0, assuming the following gate delays: 2 (a) gate 1-5 ns (b) gate 2-20 ns (c) gate 3-10 ns X 3/ Y/ Z 0 10 20 30 40 50 b) Define static 0-hazard, static 1-hazard, and dynamic hazard. t(ns)