For each of the questions you are required to do both Structural and Dataflow Verilog implementations and show that the outputs match through waveforms. You can use either Xilinx ISE or the free online tools (i) For the truth table given below, determine the function and show Verilog implementation AOCOND BAC+28+0 A+ByB+C) 100000 DOLI! ! 1 1 ! 1 ! 1 ! 1 I ! ! ABCD A+D B+C 00000 0 00011 0 00100 1 00111 0100 0 01011 1 1 01011 1000 1 0 0 1001 1 1 1 11011 1 11001 1 11011 0 0 1 0 1 0 0 1 1 1 1 1000 10 101011 100LT 110011 110111 1110 11 ! ! 1 1 1 1 1