For systems to be able to support multiple virtual machines, two levels of memory virtualization would be needed. Each of the virtual machines would control the mapping of the virtual address to the physical address. The hypervisor would then map the physical address of each of the virtual machines to the machine address. To help speed up the process of these mappings, shadow paging is used to help duplicate each of the virtual machines page tables in the hypervisor. It would intercept the virtual address to the physical address mapping changes to keep both copies consistent. To help remove some of the complexity of the shadow page tables, a hardware approach called a nested page table supports the two classes of page tables and can navigate through these tables within hardware directly. Consider the following sequence of operations: 1) Create Process 2) TLB Miss 3) Page Fault 4) Context Switch In a Word document, answer the following questions based on the criteria above: What would happen for the given operation sequence for the shadow page table and nested page table? Explain your answer. Assuming an x86 based 4-level page is in both our guest and nested page table, how many memory references would be needed to serve a TLB miss for the native and nested page table? Explain your answer. Between the metrics of TLB miss rate, TLB miss latency, page fault rate and page fault handler latency, which one of those would be the most important for shadow page table? Which are the most important for the nested page table and why? What techniques can be used to reduce page table shadowing overhead and/or reduce NPT induced overhead?