For the circuit shown in the figure below, the main components are D-Flip-Flops (not latches). Assume that at time 0, the DFFs have the data shown on the diagram stored within them (1011). a) Complete the timing diagram for the outputs Q3, Q2, Q1, Q0 (be sure to show a slight delay between input and output where necessary).

b) Examining your timing diagram carefully, what logical operation does this hardware implement?

c) Replace the DFFs with D-Latches instead and generate the timing diagram; does this circuit function according to what you described in part (b)?

GND CLK Time=0