For the code provided below identify the sequence of outputs in hexadecimal to complete the sequence table below. The output corresponds to the present state.:

Clock Period	Present State	SW	Next State	LED in Hex
1	3b010 (S2)	2b00	3b011 (S3)	8H30
2	3b011 (S3)	2b00	3b000 (S0)	8H28
3	3b000	2b00	3b???	8H [a]
4	3b???	2b10	3b???	8H [b]
5	3b???	2b10	3b???	8H [c]
6	3b???	2b10	3b???	8H [d]
7	3b???	2b10	3b???	8H [e]
8	3b???	2b11	3b???	8H [f]

Verilog Code:

module TtrfLght2( output reg [7:0] LED, // LED array , has to be register type. input [1:0] SW, // 2 bit vector for the four possible inputs combinations input clk // clock signal );

reg [2:0] state, next_state; // Define alias for state values

parameter S0=3'b000, S1=3'b001, S2=3'b010, S3=3'b011, S4=3'b100, S5=3'b101, S6=3'b110, // Not used but defined as an example S7=3'b111; // not used but defined as an example

// Change to next stat only on transition of clock,

always @(posedge clk) state <= next_state; // Future state becomes the present state

// Define next state always @(state or SW[0]) // State changes case(state) S0: case (SW) // For state validate al cases of SW 2 switches 2'b00: next_state=S1; 2'b01: next_state=S1; 2'b10: next_state=S1; 2'b11: next_state=S1; endcase S1: case (SW) // For state validate al cases of SW 2 switches 2'b00: next_state=S2; 2'b01: next_state=S4; 2'b10: next_state=S2; 2'b11: next_state=S4; endcase S2: case (SW) // For state validate al cases of SW 2 switches 2'b00: next_state=S3; 2'b01: next_state=S3; 2'b10: next_state=S3; 2'b11: next_state=S3; endcase S3: case (SW) // For state validate al cases of SW 2 switches 2'b00: next_state=S0; 2'b01: next_state=S0; 2'b10: next_state=S5; 2'b11: next_state=S5; endcase S4: case (SW) // For state validate al cases of SW 2 switches 2'b00: next_state=S2; 2'b01: next_state=S2; 2'b10: next_state=S2; 2'b11: next_state=S2; endcase S5: case (SW) // For state validate al cases of SW 2 switches 2'b00: next_state=S0; 2'b01: next_state=S0; 2'b10: next_state=S0; 2'b11: next_state=S0; endcase default next_state=S0; endcase always @(state) // Moore outputs case(state) S0: LED <= 8'H84; S1: LED <= 8'H44; S2: LED <= 8'H30; S3: LED <= 8'H28; S4: LED <= 8'H25; S5: LED <= 8'H26; S6: LED <= 8'H86; S7: LED <= 8'H87; //LED 7 indicates an undefined state output and the last 3 bits are the state value default begin LED[2:0]<=state; LED[7:3]<=5'b10000; end endcase

endmodule

- A. B. C. D. E.

[a]

- A. B. C. D. E.

[b]

- A. B. C. D. E.

[c]

- A. B. C. D. E.

[d]

- A. B. C. D. E.

[e]

A.

26

B.

28

C.

84

D.

30

E.

44