For the following 3 memory organizations 1)compute the time in cycles to load the cache and 2)compute the average memory latency

Figure a) Cache 16 words per block. bus one word wide. memory one word wide

Figure b) cache 16 words per block. bus four words wide. memory four word wide.

Figure c) cache 16 words per block. bus one word wide. memory four independent word wide.

Helpful information: The bus requires one clock to pass data. Only one thing at a time can be on the bus. The bus four words wide passes four words in one cycle. The bus one word wide can pass only one word per cycle. 

 One cycle, the bus time, is required to send the address from the CPU to the memory for all three memory organizations. The address will always be on a 16 word boundary and the memories know they are to send 16 words (the cache block size is 16 words) Every memory takes 6 cycles from the time an address is applied until the data is fetched from the memory. During this time the address can not be changed. 

 List each clock cycle (or range of clock cycles) and show what is happening or a formula for this specific case that you derive from looking at the clock cycles. "W0" stands for the word at the base address. The quote marks have the meaning 'ditto' which means same as above.

 You may write out the full sequence or figure out a formula that works for this case. Include the formula if you use one. Now that you have this, solve for questions asked at the beggining: 1)For each memory organization give the total clock cycles to load the cache. The last word of the cache must be loaded thus count the last bus cycle. This number is called the "miss penalty". 2) The miss penalty would be divided by 16, the cache block size, to get the average increase in CPI for a cache miss, assuming instructions are executed sequentially. The miss penalty divided by 16 is called the average memory latency. Note that this is less than the 6 cycles for a single memory fetch for cases b) and c).

CPU CPU CPU Multiplexor Cache Cache Cache Bus Bus Bus Memory Memory Memory Memory bank 0 ank bank 2bank 3 Memory b. Wide memory organization c. Interleaved memory organization Memory a. One-word-wide memory organization CPU CPU CPU Multiplexor Cache Cache Cache Bus Bus Bus Memory Memory Memory Memory bank 0 ank bank 2bank 3 Memory b. Wide memory organization c. Interleaved memory organization Memory a. One-word-wide memory organization