For the following ARM Assembly instruction sequence, assume that N is a variable set to 0x12341234 in RAM at address 0x20045080. For each instruction, indicate the content of the R0 and R1 CPU registers after each instruction executes. If the value cannot be known, use ??.

Note: these operations run as a sequence, instructions will affect registers used in the instructions that follow it.

Instruction Sequence RO= R1 1) LDR R0, =N 2) LDR R1, [RO] 3) MOV R0, #0x000000FF ) AND R1, RO 5) EOR R1, RO