For the following problem: A. Given a complete a HLSM diagram - including multi-bit Inputs/Outputs (for the Data Path) and single-bit Inputs/Outputs (for the FSM). B. Complete the HLSM Definition Table and the HLSM Functional Table C. If this HLSM has completed one cycle of collecting samples and computing the average of these samples, what is(are) the requirement(s) for this HLSM to take a second set of samples? List any assumptions. Note: If you are submitting a pencil-paper solution, there is no need to copy HLSM diagram. Use the RTL design process to create an alarm system that sets a single-bit output alarm to 1 when the average temperature of four consecutive samples meets or exceeds a user-defined threshold value. A 32-bit unsigned input CT indicates the current temperature, and a 32-bit unsigned input WT indicates the warning thresh- hold. Samples should be taken every few clock cycles. A single-bit input clr when 1 disables the alarm and the sampling process. Start by capturing the desired system behavior as an HLSM, and then convert to a controller/datapath. Step 1 - Capture a high-level state machine Inputs: CT, WT (32 bits); clr (bit) Outputs: alarm (bit) Local Registers: tmpo, tmpl, tmp2, tmp3, avg (32 bits) clr clr clr clr Alrmon alarm = 1 Clr alarm = '0 clr clr'*(avg>=WT) clr clr Init Sample AlrmOft clr'*(avg>=WT) alarm = '09 alarm = '09 tmp = 0 tmpl=0 tmp2 = 0 tmp3=0 avg=0 tmp = CT tmpl := tmpo tmp2 := tmp1 tmp3 := tmp2 avg = (tmp + tmp1 + tmp2 + tmp3)/4 HLSM diagram is repeated for your convenience Step 1 - Capture a high-level state machine Inputs: CT, WT (32 bits); clr (bit) Outputs: alarm (bit) Local Registers: tmpo, tmpl, tmp2, tmp3, avg (32 bits) clr clr clr clr NA Clr alarm = 0 Alrmon alarm = 1 clr clr'*(avg>=WT) clr clr Init AlrmOft clr** (avg>=WT) alarm = 0 alarm = 0 tmp = 0 tmpl=0 tmp2 = 0 tmp3 = 0 avg=0 Sample tmp = CT tmpl := tmpo tmp2 := tmpl tmp3 := tmp2 avg = (tmpo + tmpl + tmp2 + tmp3) 74 A. HLSM Definition Table Function State Description Data Path Component* * Include ALL components which have multiple-bit inputs and/or outputs. Including registers, adders, subtractors, comparators, shift registers, muxes (Figure 5.21) or subtractors, multipliers, absolute value, up counters and register files (register arrays) (Figure 5.27). HLSM diagram is repeated for your convenience Step 1 - Capture a high-level state machine Inputs: CT, WT (32 bits), cir (bit) Outputs: alarm (bit) Local Registers: tmpo, tmpl, tmp2, tmp3, avg (32 bits) clr clr clr clr NA Clr alarm = 0 AlrmOn alarmn=1 clr clr** (avg>=WT) chr clr Init Sample Alrmoft alarm = 0 clr(avg>=WT) alarm = 0 tmp = 0 tmpl=0 tmp2 = 0 tmp3=0 tmp = CT tmpl= tmpo tmp2 = tmp1 tmp3 := tmp2 avg = (tmp + tmpl + tmp2 + tmp3)/4 avg=0 B. HLSM Functional Table Data Path Component* I/O bit(s) State Init State Clr State Sample State AlrmOn State AlrmOff ld clr ld clr ld clr ld clr ld clr ld clr ld clr Id clr For the following problem: A. Given a complete a HLSM diagram - including multi-bit Inputs/Outputs (for the Data Path) and single-bit Inputs/Outputs (for the FSM). B. Complete the HLSM Definition Table and the HLSM Functional Table C. If this HLSM has completed one cycle of collecting samples and computing the average of these samples, what is(are) the requirement(s) for this HLSM to take a second set of samples? List any assumptions. Note: If you are submitting a pencil-paper solution, there is no need to copy HLSM diagram. Use the RTL design process to create an alarm system that sets a single-bit output alarm to 1 when the average temperature of four consecutive samples meets or exceeds a user-defined threshold value. A 32-bit unsigned input CT indicates the current temperature, and a 32-bit unsigned input WT indicates the warning thresh- hold. Samples should be taken every few clock cycles. A single-bit input clr when 1 disables the alarm and the sampling process. Start by capturing the desired system behavior as an HLSM, and then convert to a controller/datapath. Step 1 - Capture a high-level state machine Inputs: CT, WT (32 bits); clr (bit) Outputs: alarm (bit) Local Registers: tmpo, tmpl, tmp2, tmp3, avg (32 bits) clr clr clr clr Alrmon alarm = 1 Clr alarm = '0 clr clr'*(avg>=WT) clr clr Init Sample AlrmOft clr'*(avg>=WT) alarm = '09 alarm = '09 tmp = 0 tmpl=0 tmp2 = 0 tmp3=0 avg=0 tmp = CT tmpl := tmpo tmp2 := tmp1 tmp3 := tmp2 avg = (tmp + tmp1 + tmp2 + tmp3)/4 HLSM diagram is repeated for your convenience Step 1 - Capture a high-level state machine Inputs: CT, WT (32 bits); clr (bit) Outputs: alarm (bit) Local Registers: tmpo, tmpl, tmp2, tmp3, avg (32 bits) clr clr clr clr NA Clr alarm = 0 Alrmon alarm = 1 clr clr'*(avg>=WT) clr clr Init AlrmOft clr** (avg>=WT) alarm = 0 alarm = 0 tmp = 0 tmpl=0 tmp2 = 0 tmp3 = 0 avg=0 Sample tmp = CT tmpl := tmpo tmp2 := tmpl tmp3 := tmp2 avg = (tmpo + tmpl + tmp2 + tmp3) 74 A. HLSM Definition Table Function State Description Data Path Component* * Include ALL components which have multiple-bit inputs and/or outputs. Including registers, adders, subtractors, comparators, shift registers, muxes (Figure 5.21) or subtractors, multipliers, absolute value, up counters and register files (register arrays) (Figure 5.27). HLSM diagram is repeated for your convenience Step 1 - Capture a high-level state machine Inputs: CT, WT (32 bits), cir (bit) Outputs: alarm (bit) Local Registers: tmpo, tmpl, tmp2, tmp3, avg (32 bits) clr clr clr clr NA Clr alarm = 0 AlrmOn alarmn=1 clr clr** (avg>=WT) chr clr Init Sample Alrmoft alarm = 0 clr(avg>=WT) alarm = 0 tmp = 0 tmpl=0 tmp2 = 0 tmp3=0 tmp = CT tmpl= tmpo tmp2 = tmp1 tmp3 := tmp2 avg = (tmp + tmpl + tmp2 + tmp3)/4 avg=0 B. HLSM Functional Table Data Path Component* I/O bit(s) State Init State Clr State Sample State AlrmOn State AlrmOff ld clr ld clr ld clr ld clr ld clr ld clr ld clr Id clr