For the following three questions, you will be designing a memory subsystem for a computer with an $8-$bit data bus and a $16-$bit address bus. The memory subsystem consists of a combination of ROM and RAM, implemented either as individual memory chips or as arrays of memory chips, with each type of memory occupying a portion of the available $64$K address space. Your partial address decoding logic must ensure that these chips are active only within the range of addresses described below.

$1)(10$ points$)$ The first memory device in this system is an $8$K firmware ROM corresponding to the memory address range $$0000$ to $$1$FFF$.$ Show the logic to generate a CE signal$($s$)$ for this ROM, which should be active low, if one $8$K x $8$ ROM chip is used.Draw and test the complete circuit in Logisim within the $"$Q$1"$ subcircuit in the provided file, using traditional logic gates.

$($Hint: Note that an $8K8$ memory chip has a capacity of $8192$ bytes; since only one of these chip is needed to create a single $8K8$ ROM memory unit, only one CE signal is needed for this chip.$)$