for the following VHDL code, design a testbench code, double check it is working, I need the output waveform

// Library declaration library IEEE; use IEEE.STD_LOGIC_1164.ALL; // Entity declaration entity two_way_traffic_light is Port ( clk: in STD_LOGIC; reset: in STD_LOGIC; north_green: out STD_LOGIC; north_yellow: out STD_LOGIC; north_red: out STD_LOGIC; south_green: out STD_LOGIC; south_yellow: out STD_LOGIC; south_red: out STD_LOGIC); end two_way_traffic_light; // Architecture declaration architecture Behavioral of two_way_traffic_light is -- Signal declaration signal count: integer range 0 to 1023 := 0; signal north_light_state, south_light_state: integer range 0 to 3 := 0; begin // Clocked sequential logic process (clk, reset) begin if reset = '1' then count <= 0; -- Reset count to 0 if reset is high elsif clk'event and clk = '1' then count <= count + 1; -- Increment count on every rising edge of clk end if; end process; // State machine process (count) begin case count is when 0 => north_light_state <= 0; south_light_state <= 0; when 1 to 170 => north_light_state <= 1; south_light_state <= 1; when 171 to 340 => north_light_state <= 2; south_light_state <= 2; when 341 to 510 => north_light_state <= 3; south_light_state <= 3; when 511 to 680 => north_light_state <= 2; south_light_state <= 2; when 681 to 850 => north_light_state <= 1; south_light_state <= 1; when 851 to 1023 => north_light_state <= 0; south_light_state <= 0; when others => null; end case; end process; // Light state assignment north_green <= '1' when north_light_state = 1 else '0'; north_yellow <= '1' when north_light_state = 2 else '0'; north_red <= '1' when north_light_state = 3 else '0'; south_green <= '1' when south_light_state = 1 else '0'; south_yellow <= '1' when south_light_state = 2 else '0'; south_red <= '1' when south_light_state = 3 else '0'; end Behavioral;