For the following VHDL code, draw the corresponding circuit diagram and explain the purpose of the circuit. Code 1 library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity circuit1 is port(A,B,C,D: in std_logic := '1'; Y: out std_logic); end circuit; architecture one of circuit is begin Y <= A and B and C and D; end circuit; Code 2 library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; entity circuit2 is port( a,b : in unsigned(2 downto 0); a_e_b : out std_logic; a_l_b : out std_logic; a_g_b : out std_logic ); end circuit2; architecture gate_level of circuit2 is signal temp1,temp2,temp3,temp4,temp5,temp6,temp7,temp8,temp9:std_logic:= '0'; BEGIN temp1 <= not(a(2) xor b(2)); --XNOR gate with 2 inputs. temp2 <= not(a(1) xor b(1)); --XNOR gate with 2 inputs. temp3 <= not(a(0) xor b(0)); --XNOR gate with 2 inputs. temp4 <= (not a(2)) and b(2); temp5 <= (not a(1)) and b(1); temp6 <= (not a(0)) and b(0); temp7 <= a(2) and (not b(2)); temp8 <= a(1) and (not b(1)); temp9 <= a(0) and (not b(0)); a_eq_b <= temp1 and temp2 and temp3; -- for a equals b. a_le_b <= temp4 or (temp1 and temp5) or (temp1 and temp2 and temp6); a_gt_b <= temp7 or (temp1 and temp8) or (temp1 and temp2 and temp9); end gate_level;