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For the next three problems, we will consider the addition of an L 2 cache to P 1 to presumably make up for its limited

For the next three problems, we will consider the addition of an L2 cache to P1 to presumably make up
for its limited L1 cache capacity. Assume main memory access takes 70ns and memory accesses are
36% of all instructions.
The data for L1 cache is as follows:
The L2 miss rate indicated is its local miss rate.
L2 Size: 1MB
L2 Miss Rate: 95%
L2 Hit Time: 5.62ns
What is the AMAT for P1 with the addition of an L2 cache? Is the AMAT better or worse with the L2
cache?
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