For the vhdl I just need the code also for the test bench

Design a state machine that can detect the sequence 101101 in a stream of serial data. The output should go high when the correct sequence is detected. You should take the following steps to implement and test the state machine: Step 1 Draw the State Diagram. Step 2 Create the Transition Table Step 3 Develop the excitation equations. Step 4 Implement the state machine using VHDL Step 5 Develop a testbench for the state machine. The testbench should generate the following