From the network graph of a circuit, an extracted partition of the network is represented using

the following Boolean function

$f=A{B}^{\text{'}}C+BD{E}^{\text{'}}+AE$

Assuming NAND and Invert as base functions, perform cell library binding by minimizing the

delay as the cost. Do not eliminate intermediate inverters while drawing the pattern graph. The

subgraph is driving another subgraph of load $4.$ The inputs A and B are ready at time $0,$ inputs C

and $D$ at time $3$ and $E$ at $6.$

The cell library contains inverter $($delay $=1+$ load, load$=1),2$ input NAND $($delay $=2+$ load,

load$=2),2$ input AND $($delay$=-3+$load, load$=2)$ and $2$ input OR $($delay$=3+$load, load$=2).$