Generic FSM with 1 bit serial x 1) (Lectures 9 and 10) Let's do a finite state machine that detects the sequence 101 on serial one-bit input x. One-bit output Z is 0 unless the 101 has been detected. Z should be one in any case in which previous 3 inputs are 101, including overlapping cases. Reset =1 should take the finite state machine back to the initial state. 1 X {Q,x} m Sel This is a block diagram of a generic FSM. Assume a Moore Model (Remember in a Moore model states alone combinatorially determine output Z). An n D Register Bn N:1 cn MUX reset If it takes 4 states to make this machine then n = 2 And if you do {Q,x} m = 3 n Q Z Logic What to do A) draw a state diagram for this machine B) create a state assignment table for your state machine C) create a state transition table for your state machine D) find the logic to get Z from the state Q 2) Continue problem 1 A) Write a System Verilog multiplexer module for your state machine, parameterize input and output array sizes B) Write a System Verilog D register module for your state machine, parameterize input and output array sizes C) Write a System Verilog module instantiating your multiplexer and register and using logic to determine output Z. Your inputs should be clock, reset, x, and output should be Z. D) Write a testbench and run it with the sequence x = 000010010101011 and display the inputs (x) and outputs (Z) on each positive clock edge to the transcript window E) Port your FSM to Quartus and capture the RTL netlist image