give me the solution

rroolern 5. (Y points) Synchronization Load-reserved (LR) and store conditional (SC) instructions can be used to implement atomic memory operations in RISC-V. Their usage and description are given below: I r. w rd, (rsl) # LR loads a word from the address in rsl, places the signextended value in rd, and registers a reservation on the memory address sc.w rd, rs2, (rsl) # SC writes a word in rs2 to the address in rsl, provided a valid reservation still exists on that address. SC writes zero to rd on success or a nonzero code on failure Fill in the lines below to implement compare-and-swap function. Compare-and-swap function compares the value at a memory location with an expected value and if they are equal, swap the value at the memory location with the desired value. The function returns a zero on success or a value of 1 on failure. # When the function is called, x 10 holds the address of memory location # XII holds the expected value x 12 holds the desired value # When the function returns, # x 10 holds return value, 0 if successful, 1 otherwise cas : j alr xor 0 (x 1) fail: addi x 10, x0, 1 j alr x0, 0 (x 1) Refer to the following RISC-V ISA reference as needed. Base Int errnstructions 32 64 128 Name Fmt RV 32 64 128 1 Base Base Inte er Instructions 32 64 128 Name Fmt Ca o RV 32 64 128 1 Base Loads Load Byte Load Halfword Load Word Load Byte Unsigned Load Half ned Stores Store Byte Store Halfword Store Word Shift Left Shifts Shift Left Immediate Shift Right Shift Right Immediate Shift Right Shift Right Arith Imm ADD Arithmetic ADD Immediate SUBU-act Load upper Imm Add U Imm to PC I I I 1 I S S S R I R I R I R I R U U rd, rsl,l LB rd, rsl,lm LB L{WIDIQ} rd, rsi,im rd, rsl, ISV L H W D U rd rsl in rsi, rs2 , in SB rsl rs2 i SLL{ IwID) SLLI{ lwlD} SRL{IWID} SRLI{IWID} SRA{ lwlD} SRAI W D ADD( IWI D} rd,rsijrs2 ADDI{IWID} SUB( lwlD) rd, rs1,rs2 rd, LUI rd in AUIPC XOR Logical XOR Immediate OR OR Immediate AND AND Immediate Set < Compare Set < Immediate Set < Unsigned Set < Imm Unsi ed Branches Branch = Branch Branch < Branch Branch < Unsigned Branch uns ned Jump & Link Jum & Link R ister 6 R XOR I XORI R OR 1 ORI R AND ANDI R SLT I SLTI R SLTU I SLTIU SB BEQ SB BNE SB BLT SB BGE SB BLTU SB BGEU UJ JAL I JALR rd. rsi,rs2 rd, rsl inn rd, rsi , rs2 rd rsl inn rd, rs1,rs2 rd, ral,im rd rsl im rsi, rs , rs2 , in rsl rs2 rd , im rd rsl