Given a T flip flop with a synchronous reset in behavioral verilog:

module TFF_Sync(T, clk, rst, Q);

input T, clk, rst;

output reg Q;

always @(posedge clk)

begin

if(rst)

Q <= 0;

else if(T == 1)

Q <= ~Q;

else

Q <= Q;

end

endmodule

a. implement a D flip flop with a synchronous reset using the T flip flop provided above in behavioral verilog