Given the circuit shown above ``R-to-R Transfer Controlled by MUX.'' Fill in the rest of the table. T0 T1 T2 T3 T4 T5 T6 IN_R0 3 5 7 9 11 13 15 IN_R1 0 2 4 6 8 10 12 OUT_R0 OUT_R1 K1 0 0 1 0 0 1 1 K2 1 0 0 0 1 0 1 ENABLE (LOAD) IN_R2 OUT_R2 

4, K1 Load 0 4 MUX 4 R1 (a) Block diagram K1 REGISTER LOAD 2-to-1 MUX C RO REGISTER LOAD c R2 R1 REGISTER LOAD Cloc C R1 (b) Detailed logic