Given the following single-cycle "Minimal MIPS" datapath, answer the questions that follow: Diagram or explain the hardware changes needed to support the following instructions. Be sure to account for both the data hardware and the control signal changes needed. jr (jump to register, copies the value of a register into PC) jal (jump and link; copies the value of PC+4 into a register, then jumps to a new address) Now we want to convert our datapath to a multi-cycle (but NOT pipelined) version. For both those instructions (jr and jal), explain what, if anything, they would do during the EX, MEM, and WB phases of execution