Given the following VHDL :

Fill in the blanks 1-12 the correct answer (you have to answer the blanks without knowing the options)

library useles logic1164all entity port a: instd logic b:instd logic C: instd logic Tout std logic yout std logic end entity fuc? architecture structure of func2b component or gatels port xy in std logic zout std logic end component component and gate is port (xyIn std logic zout sidlogi end component component or gates port ky instd logic zout sidlogie end component signal tmp_mbstdlopi signal tmpy Flogic signal tmp_abod logic begin gate type o portmap Y portmap gate type port map y > z> tmp_axb ): 13:and_gate port map Log impy X Y- 21 , 3: & tmpat gate type @ port map X> tmp axb y> 12 ): end architecture structures library useles logic1164all entity port a: instd logic b:instd logic C: instd logic Tout std logic yout std logic end entity fuc? architecture structure of func2b component or gatels port xy in std logic zout std logic end component component and gate is port (xyIn std logic zout sidlogi end component component or gates port ky instd logic zout sidlogie end component signal tmp_mbstdlopi signal tmpy Flogic signal tmp_abod logic begin gate type o portmap Y portmap gate type port map y > z> tmp_axb ): 13:and_gate port map Log impy X Y- 21 , 3: & tmpat gate type @ port map X> tmp axb y> 12 ): end architecture structures