; GPIO base addresses of port D and E

gpioFbase EQU $0$x$4005$D$000$

gpioEbase EQU $0$x$4005$C$000$

gpioAbase EQU $0$x$40058000$

gpioDbase EQU $0$x$4005$B$000$

; PWM $0$ base adress

pwm$0$base EQU $0$x$40028000$

; PWM register offsets

pwmcc EQU $0$x$...$ ; TO DO

pwm$0$ctl EQU $0$x$...$ ; TO DO

pwm$0$gena EQU $0$x$...$ ; TO DO

pwm$0$genb EQU $0$x$...$ ; TO DO

pwm$0$load EQU $0$x$...$ ; TO DO

pwm$0$cmpa EQU $0$x$...$ ; TO DO

pwmenable EQU $0$x$...$ ; TO DO

; ADC $0$ base adress

adc$0$base EQU $0$x$40038000$

; ADC register offsets

adcactss EQU $0$x$000$

adcemux EQU $0$x$014$

adcssmux$3$ EQU $0$x$0$A$0$

adcssemux$3$ EQU $0$x$0$B$8$

adcssctl$3$ EQU $0$x$0$A$4$

adcssfifo$3$ EQU $0$x$0$A$8$

adcpssi EQU $0$x$028$

; GPIO offsets, least significant $8$ bits $($mostly$)$

gpioData EQU $0$x$000$ ; 'data' add relevant gpio data mask offset for masking, to read or write all values add $0$x$3$FC to base which is sum of all bit constants

gpioDir EQU $0$x$400$ ; 'direction' $0$ for inp, $1$ for out, inp by default

gpioAfsel EQU $0$x$420$ ; 'alterrnate function select' $0$ for standard gpio and gpio register used in this time, $1$ for path over selected alternate hardware function, hardware function selection is done by gpiopctl register control, $0$ default

gpioPctl EQU $0$x$52$C ; 'port control' see documentation

gpioLock EQU $0$x$520$ ; to unlock $0$x$4$c$4$f$434$b shoulb be written, any other write locks back, enables write access to gpiocr

gpioCr EQU $0$x$524$ ; 'commit' gpioafsel, pur, pdr$,$ den can only be changed with setting bit in cr$,$ only modified when unlock gpiolock

gpioAmsel EQU $0$x$528$ ; 'analog mode select' only valid for pins of adc, set for analog,

gpioDen EQU $0$x$51$c ; 'digital enable'

; GPIO data mask offset constant, $[9$:$2]$ in address are ussed for $[7$:$0]$ bits masking

; to only write to pin $5$ of any port 'five' offset should be added to gpiodata

; to only write to pins $2$ and $5$ of any port data should be written dataregister address $+$ 'two'$+$'five' offset address remainings left unchange in output $0$ in input mode

gpioDataZero EQU $0$x$004$

gpioDataOne EQU $0$x$008$

gpioDataTwo EQU $0$x$010$

gpioDataThree EQU $0$x$020$

gpioDataFour EQU $0$x$040$

gpioDataFive EQU $0$x$080$

gpioDataSix EQU $0$x$100$

gpioDataSeven EQU $0$x$200$

; GPIO clck gating register

; default $0$ and disabled by clck blocking

; bit #$0$ for port A and #$1$ for port B should be set to enable ports

; after setting $3$ clck cycle is needed to reach port registers properly

rcgcgpio EQU $0$x$400$FE$608$

rcgcpwm EQU $0$x$400$FE$640$

rcgadc EQU $0$x$400$FE$638$

delayData EQU $0$x$40000$ ; use this delay data as the time spent on one frequency mode

highFreq EQU $0$x$00$FFF ; use this value for high frequency mode

lowFreq EQU $0$x$01$FFF ; use this value for low frequency mode

AREA MYCODE, CODE

ALIGN

ENTRY

EXPORT $\_\_$main

$\_\_$main

NOP

BL initialize

loop

LDR R$1,=$adc$0$base

ADD R$1,$ R$1,$ #adcpssi

LDR R$0,[$R$1]$

ORR R$0,$ R$0,$ #$0$x$08$ ; trigger ADC to start a conversion

STR R$0,[$R$1]$

LDR R$1,=$adc$0$base

ADD R$1,$ #adcssfifo$3$

LDR R$0,[$R$1]$ ; read $12-$bit ADC output data, the converted value is now in R$0$

; TO DO: write the most significant $8$ bit of converted value to port D

; TO DO: make necessary changes on the PWM registers so that the buzzer keeps changing its frequency,

; also control the volume of the buzzer with ADC output value

; don't worry about the PWM$-$buzzer connection, they will be connected physically

B loop

initialize

; enable clck for ports A$,$ D$,$ E and F

LDR R$1,=$rcgcgpio

LDR R$0,[$R$1]$

ORR R$0,$ R$0,$ #$0$x$39$ ;

STR R$0,[$R$1]$

NOP

NOP

NOP

LDR R$1,=$rcgcpwm ; enable PWM clock

LDR R$0,[$R$1]$

ORR R$0,$ R$0,$ #$0$x$01$ ; PWM$0$

STR R$0,[$R$1]$

NOP

NOP

NOP

LDR R$1,=$rcgadc ; enable ADC clock

LDR R$0,[$R$1]$

ORR R$0,$ R$0,$ #$0$x$01$ ; ADC$0$

STR R$0,[$R$1]$

NOP

NOP

NOP

; port A init

LDR R$1,=$gpioAbase

ADD R$1,$ R$1,$ #gpioDir

LDR R$0,[$R$1]$

ORR R$0,$ R$0,$ #$0$xFF

STR R$0,[$R$1]$

LDR R$1,=$gpioAbase

ADD R$1,$ R$1,$ #gpioAfsel

LDR R$0,[$R$1]$

BIC R$0,$ #$0$xFF

STR R$0,[$R$1]$

LDR R$1,=$gpioAbase

ADD R$1,$ R$1,$ #gpioDen

LDR R$0,[$R$1]$

ORR R$0,$ R$0,$ #$0$xFF

STR R$0,[$R$1]$

; port D init

LDR R$1,=$gpioDbase

ADD R$1,$ R$1,$ #gpioDir

LDR R$0,[$R$1]$

ORR R$0,$ R$0,$ #$0$xFF

STR R$0,[$R$1]$

LDR R$1,=$gpioDbase

ADD R$1,$ R$1,$ #gpioAfsel

LDR R$0,[$R$1]$

BIC R$0,$ #$0$xFF

STR R$0,[$R$1]$

LDR R$1,=$gpioDbase

ADD R$1,$ R$1,$ #gpioDen

LDR R$0,[$R$1]$

ORR R$0,$ R$0,$ #$0$xFF

STR R$0,[$R$1]$

; port F init

LDR R$1,=$gpioFbase

ADD R$1,$ R$1,$ #gpioDir

LDR R$0,[$R$1]$

ORR R$0,$ R$0,$ #$0$xFF

STR R$0,[$R$1]$

LDR R$1,=$gpioFbase

ADD R$1,$ R$1,$ #gpioAfsel

LDR R$0,[$R$1]$

ORR R$0,$ #$0$x$01$ ; set for PWM$0$

STR R$0,[$R$1]$

LDR R$1,=$gpioFbase

ADD R$1,$ R$1,$ #gpioPctl

LDR R$0,[$R$1]$

ORR R$0,$ #$0$x$06$ ; write $6$ to select PWM from alternate functions

STR R$0,[$R$1]$

LDR R$1,=$gpioFbase

ADD R$1,$ R$1,$ #gpioDen

LDR R$0,[$R$1]$

ORR R$0,$ R$0,$ #$0$xFF

STR R$0,[$R$1]$

; port E init

LDR R$1,=$gpioEbase

ADD R$1,$ R$1,$ #gpioAfsel

LDR R$0,[$R$1]$

ORR R$0,$ #$0$x$08$

STR R$0,[$R$1]$

LDR R$1,=$gpioEbase

ADD R$1,$ R$1,$ #gpioDen

LDR R$0,[$R$1]$

BIC R$0,$ R$0,$ #$0$x$08$

STR R$0,[$R$1]$

LDR R$1,=$gpioEbase

ADD R$1,$ R$1,$ #gpioAmsel

LDR R$0,[$R$1]$

ORR R$0,$ R$0,$ #$0$x$08$

STR R$0,[$R$1]$

; ADC init

LDR R$1,=$adc$0$base

ADD R$1,$ R$1,$ #adcactss ; bit field $[3$:$0]->[$SS$3$ enable, SS$2$ enable, SS$1$ enable, SS$0$ enable$]$

LDR R$0,[$R$1]$

BIC R$0,$ R$0,$ #$0$x$08$

STR R$0,[$R$1]$

LDR R$1,=$adc$0$base

ADD R$1,$ R$1,$ #adcemux ; bit field $[15$:$0]->$ SS$3[0$x$0=$processor triggered$($adcpssi$)],[$SS$2$ trigger$],$ SS$1$ trigger, SS$0$ trigger

LDR R$0,[$R$1]$

BIC R$0,$ R$0,$ #$0$xF$000$

STR R$0,[$R$1]$

LDR R$1,=$adc$0$base

ADD R$1,$ R$1,$ #adcssmux$3$ ; bit field $[3$:$0]->$ SS$3$ input select $($if adcssemux$3$ bit is set, there is an offset of $16)$

LDR R$0,[$R$1]$

BIC R$0,$ R$0,$ #$0$xF

STR R$0,[$R$1]$

LDR R$1,=$adc$0$base