GPR Tmp1 MAR MDR IR PC PSW Y ALU Z Tmp2 Referencing the states outlined in the Quiz Instructions, develop a finite state machine for the fetch decode execute cycle given that correct instruction execution occurs as follows: 1. normal execution follows the standard fetch/decode/execute cycle 2. instructions with IR.T1=1 require both operand decode alternatives to be performed 3. instructions with IR.T1=0 and IR.T2=1 require only that the second opcode alternative be performed 4. instructions with IR.T1=0 and IR.T2=0 are executed without any opcode states 5. instructions with IR.OPCODE=12 and the PSW.N=0 are not executed 6. after instruction fetch, all instructions with IR.OPCODE=14 and the PSW.P=0 are immediately trapped to T1 Instruction processing never stops. You need to describe the conditions governing the state transitions for this machine. You should write the transitions as: From state -> To state: condition written as a boolean expression GPR Tmp1 MAR MDR IR PC PSW Y ALU Z Tmp2 Referencing the states outlined in the Quiz Instructions, develop a finite state machine for the fetch decode execute cycle given that correct instruction execution occurs as follows: 1. normal execution follows the standard fetch/decode/execute cycle 2. instructions with IR.T1=1 require both operand decode alternatives to be performed 3. instructions with IR.T1=0 and IR.T2=1 require only that the second opcode alternative be performed 4. instructions with IR.T1=0 and IR.T2=0 are executed without any opcode states 5. instructions with IR.OPCODE=12 and the PSW.N=0 are not executed 6. after instruction fetch, all instructions with IR.OPCODE=14 and the PSW.P=0 are immediately trapped to T1 Instruction processing never stops. You need to describe the conditions governing the state transitions for this machine. You should write the transitions as: From state -> To state: condition written as a boolean expression