HDL LILY TOP Use He. P3(b) (20) Complete the following partial VHDL model for the above state machine. Assume So-"00". 51-"01", and S-"10 Any white space can be used to add any other code you feel is necessary and appropriate. All existing code is correct, but the coding may be either inefficient or not straightforward. architecture behavioral of sequencer is signal state, nextState: unsigned (1 downto 0); begin --process responsible for combinational logic process (X, Y, State) begin Z case X & Y us -- non-locally static, accept as is when "00" => next State when "10" => when "11" => when others => end case; when "01" => if x='1' and Y='1' then next State case X & Y us -- non-locally static, accept as is when "00" => next State when "10" => when "11" => when others => end case; when "01" => if x='1' and Y='1' then next State