Hello, I need some help writing/understanding VHDL...

I have this code for a 4-Bit Shift Register..

The simulated results is supposed to look like this:

..but when I put the code into Vivado, I get this:

Could someone explain to me why the code is not giving me the same results? I'm assuming it is because I don't have a testbench? If that is the case, could someone tell/guide me how I need to write a testbench, and what would a testbench code look like for the code that is displayed in this problem?

Thank you very much in advance!

library IEEE; use IEEE.STD LOGIC 1164.ALL use IEEE.STD LOGIC ARITH.ALL use IEEE. STD_LOGIC_UNSIGNED.ALL; entity Shift register VHDL is port( clk: in std logic; L: in std_logic; w: in std_logic; Output: out std_logic_vector(3 downto 0); Input: in std_logic_vector( 3 downto 0)); -new data to shift in end Shift register VHDL architecture Behavioral of Shift register VHDL is begin process variable temp: std logic vector (3 downto 0) begin wait until rising edge (clk); temp := Input; if L='1' then for i in 0 to 2 loop temp(1) := temp(1+1); end Loop; temp(3) := w; end if; Output