Hi, check the answers that I have for this problem. Please correct any mistakes that I may have and provide explanation, Thanks.

3. [8 points] Suppose we have the following latencies for various datapath units. Latency in ps 200 50 50 25 150 120 10 Resource I Mem PC Add Branch Add All MUXs REGs ALU SIGNEXT Shift Left 2 D Mem 250 70 ALU Control (a) [4 pts] Calculate the total latency for a load (b) [4 pts] If we switch to a pipeline architecture, show your work in calculating these values. SOx1R soors instruction. So2oo 5+1S0 +25+Ino so+S t ISOSs (1) what is the clock cycle time ??sors (ii) what is the total latency for a load instruction? [Note for Instructor CRIT] PCSre Add ALU Shift left 2 RegWrite Instruction (25.21] Read PCH/ Read register 1 Read Read register 2 MemWrite instruction [20:16] data 1- ALUSrc Zero MemtoReg M Write Read Instruction Instruction (1511register data2 memory result? Address Read Write data Registers Data Instruction [15:0] 16 Sign. 32 extend ALU MemRead Instruction (5:0] ALUOp