Hi, I would appreciate help with this computer architecture question. Thank you and have a nice day!

Suppose that memory addresses are 16 bits and cache lines are 128 bytes in size. The system uses a single two-way set-associative cache of 8 lines. Starting with the initial cache state shown below, the system performs accesses to the following sequence of memory addresses:

1. 0xAC7D

2. 0x7E9D

3. 0x7699

4. 0x62BB

5. 0x7695

6. 0x39F1

7. 0x76DC

8. 0x98D7

Addresses of memory accesses

Line #	Tag
0	0x12
1	0x45
2	0x3B
3	0x58
4	0x58
5	0x0C
6	0x1E
7	0x3E

Initial cache state (your answers to (a) and (b) should be shown in this format)

1. How many bits are the offset, set number, and tag fields of memory addresses in this cache?

2. Give the set number and tag (in hexadecimal) for each of the memory addresses that are accessed.

3. If the cache is using the LRU replacement algorithm, say whether each access is a hit or miss. Show the final state of the cache in a table similar to the example below.

4. Repeat (a) using FIFO replacement instead.