Hi this is a problem related to memory hierarchy from my computer architecture class.

Question 4 Memory Hierarchy a. (5 marks) Consider a program that accesses a 10,000-word array of 32-bit integers in reverse order i.e. using indices 9999, 9998, ..., 1, 0. Assuming a 64 KB direct-mapped cache with 4- word blocks. Supported by a clear explanation, give an estimate of the miss rate due to b. (5 marks) Explain why,in general, cache block sizes which are too small or too large will lead c. (5 marks) Explain the difference between a write-through and a write-back scheme. Which d. (5 marks) Explain the differences between a cache miss and a page fault, particularly the e. (5 marks) Explain using an example the issue of cache coherence. Is it an issue for single core compulsory misses, capacity misses and conflict misses to higher miss rates would be most appropriate for the virtual memory to disk interface? response time required and how they are handled in a modern computer. processors