Hint: You have to add Ainvert, Binvert and Less in your enhanced full bit adder, your

final Op should be a $4$ bit input signal. Op$[0]$ will be Ainvert, Op$[1]$ will be Bnegate,

Op$[2$:$3]$ will be selection input to the Mux. We can also detect the overflow by checking

whether the CarryIn and CarryOut of the most significant bit are different, such as xoring

as $C30$ and Cout $($e$.$g$.$ assign $Ov=C{30}^{C}31.$ Taking xor of overflow and Result of the

most significant bit can give us LessThan $($assign Set $=O{v}^{?}$ Result$[31])$ which should be

connected to LESS input of the least significant bit of $32$ bit ALU. An instance of $1-$bit

ALU may look like full$\_$adder$\_$en FA$2($A$[1],$ B$[1],1\text{'}$b$0,$ C$0,$ Op$[0],$ Op$[1],$ Op$[2$:$3],$

Result$[1],$ C$1)$;$.$ And Set can replace $1\text{'}$b$0$ in LT position in case of the first $1-$bit ALU.

full$\_$adder$\_$en FA$1($A$[0],$ B$[0],$ Set, Op$[1],$ Op$[0],$ Op$[1],$ Op$[2$:$3],$ Result$[0],$ C$0)$;$.$

full$\_$adder$\_$en FA$2($A$[1],$ B$[1],1\text{'}$b$0,$ C$0,$ Op$[0],$ Op$[1],$ Op$[2$:$3],$ Result$[1],$ C$1)$;$.$

module alu$16($A$,$B$,$Cin,Op$,$ Result, Cout$)$; points $=254$ Design an $32$ bit ALU in Verilog with OR$,$ AND, NOR, ADD, SUB,

SLT logic as shown in the figure based on the given models. Attach screen$-$shots of

outputs, answers to the questions, verilog code. Moreover, submit your code as

separate files so that the grader can test it$.$ Check the tutorial at the end.

a$.$ Write your verilog program for the $32$ bit ALU

b$.$ Discuss what type of Verilog models $($e$.$g$.$ Structural, Dataflow, hierarchical etc.$)$

you have used and why? Also show your comments for all the parameters such

as input and output ports, connections, instances of other lower level modules

etc.

c$.$ Write a testbench for the $32$ bit ALU. Use the tutorial $($at the end$)$ for writing your

testbench. In the case of random ALUcontrol, use only five control signals that

can be tested

d$.$ Compile and run your simulations in ModelSIm. Test whether your results are

correct.