31 - Consider an array A containing 16 bit signed numbers stored in one embedded memory with 256 locations with 16 bits per location. The array data is stored in "linear" fashion, with element A[i] stored in location "i". Design a digital circuit that computes the maximum element in the array. This maximum element is stored into a register. Assume that the memory is a single-port RAM with one clock cycle latency. The aim is to reduce the number of clock cycles required to complete the calculation. Write/simulate the Verilog code. 32 - Repeat problem 31 with a dual-port RAM with one clock cycle latency.