How to get my makefile to properly compile

# Logan Cumming Turner, 1001414779 SRC1 = Code2_1001414779.c SRC2 = MyLib.c OBJ1 = Code2_1001414779.o OBJ2 = MyLib.o EXE = Code2_1001414779.e

HFILES = MyLib.h

CFLAGS = -g

all : Code2_1001414779.e

Code2_1001414779.e: Code2_1001414779.o MyLib.o #gcc $(CFLAGS) $(OBJ1) $(OBJ2) -o $(EXE) gcc -c -g Code2_1001414779.c -o Code2_1001414779.o Code2_1001414779.o : Code2_1001414779.c MyLib.h #gcc -c $(CFLAGS) $(SRC1) -o $(OBJ1) gcc -c -g MyLib.c -o MyLib.o

MyLib.o : MyLib.c MyLib.h #gcc -c $(CFLAGS) $(SRC2) -o $(OBJ2) gcc -g Code2_1001414779.o MyLib.o -o Code2_1001414779.e

This is my make file, but when I run it in unix I get these errors

makefile:31: warning: overriding commands for target `Code2_1001414779.e' makefile:16: warning: ignoring old commands for target `Code2_1001414779.e' makefile:34: warning: overriding commands for target `Code2_1001414779.o' makefile:20: warning: ignoring old commands for target `Code2_1001414779.o' makefile:37: warning: overriding commands for target `MyLib.o' makefile:25: warning: ignoring old commands for target `MyLib.o'

How can I change my code to make this work

If it helps, this is the blank template

SRC1 = Code2_1000074079.c SRC2 = MyLib.c OBJ1 = $(SRC1:.c=.o) OBJ2 = $(SRC2:.c=.o) EXE = $(SRC1:.c=.e)

HFILES = MyLib.h

CFLAGS = -g

all : $(EXE)

$(EXE): $(OBJ1) $(OBJ2) gcc $(CFLAGS) $(OBJ1) $(OBJ2) -o $(EXE)

$(OBJ1) : $(SRC1) $(HFILES) gcc -c $(CFLAGS) $(SRC1) -o $(OBJ1)

$(OBJ2) : $(SRC2) $(HFILES) gcc -c $(CFLAGS) $(SRC2) -o $(OBJ2)