I am having trouble with this assignment. If someone could help me with the main module or a clue how to do it please.

It is Systemverilog and we are using Quartus for the project.

MDR AC opcode value STORE, MEM ALU LOAD-PC The ports you should implement for the ALU are: . MDR an 8-bit bus for the Memory Data Register (an operand) AC-an 8-bit bus for the Accumulator (an operand) Z-an 8-bit bus for the result * opcode an 8-bit bus for the opcode value an 8-bit bus for the value or address STORE MEM a 1-bit control line LOAD PC - a 1-bit control line The opcode controls how the other inputs (MDR, AC, and value) are used to set output values (Z, STORE_MEM, LOAD_PC). The specific opcodes you should implement are: Opcode 0000_0000 0000 0001 0000 0010 0000 0011 0000 0100 0000 0101 0000 0110 0000 0111 0000 1000 0000 1001 0000 1010 0000 1011 Assembly NOP LOAD address LOADI value STORE address CLR ADD address ADDI value SUBT address SUBTI value NEG address NOT address AND address Operation No operation Z MDR Z value Assert STORE MEM Z AC + MDR Z AC + value Z AC-MDR Z AC-value Z NOT MDR Z AC AND MDR MDR AC opcode value STORE, MEM ALU LOAD-PC The ports you should implement for the ALU are: . MDR an 8-bit bus for the Memory Data Register (an operand) AC-an 8-bit bus for the Accumulator (an operand) Z-an 8-bit bus for the result * opcode an 8-bit bus for the opcode value an 8-bit bus for the value or address STORE MEM a 1-bit control line LOAD PC - a 1-bit control line The opcode controls how the other inputs (MDR, AC, and value) are used to set output values (Z, STORE_MEM, LOAD_PC). The specific opcodes you should implement are: Opcode 0000_0000 0000 0001 0000 0010 0000 0011 0000 0100 0000 0101 0000 0110 0000 0111 0000 1000 0000 1001 0000 1010 0000 1011 Assembly NOP LOAD address LOADI value STORE address CLR ADD address ADDI value SUBT address SUBTI value NEG address NOT address AND address Operation No operation Z MDR Z value Assert STORE MEM Z AC + MDR Z AC + value Z AC-MDR Z AC-value Z NOT MDR Z AC AND MDR