I am struggling to get this problem. I have a "code" that will run in verilog but it will not change states. If you could please help that would be awesome, I have spent several hours trying to get a running code and I dont know what to change.

Thank you.

Design a sequential circuit that has a one bit input A and a one bit output Y. The circuit produces Y=1 when the previous two values of A are 00 or 11. Otherwise, Y=0. (a) Implement the design using a Moore-type Finite State Machine (FSM): i. Draw the state transition diagram for the sequential circuit above ii. Generate the state transition table for the sequential circuit above iii. Implement the design in Verilog iv. Write a testbench to test the design against the following input sequences 1101000111, 1010101010. The rightmost bit of the input sequence is presented to the circuit first, followed by the bits to its left. (b) Implement the design using a Mealy-type FSM and repeat the steps(i - iv). Design a sequential circuit that has a one bit input A and a one bit output Y. The circuit produces Y=1 when the previous two values of A are 00 or 11. Otherwise, Y=0. (a) Implement the design using a Moore-type Finite State Machine (FSM): i. Draw the state transition diagram for the sequential circuit above ii. Generate the state transition table for the sequential circuit above iii. Implement the design in Verilog iv. Write a testbench to test the design against the following input sequences 1101000111, 1010101010. The rightmost bit of the input sequence is presented to the circuit first, followed by the bits to its left. (b) Implement the design using a Mealy-type FSM and repeat the steps(i - iv)