I have VHDL code for a 4 bit and 16 bit Carry Look Ahead Adder, but I need to create a 32bit Carry Look Ahead Adder from them. Also if possible, test bench code would be great!

Code is as follows:

c-- 4-bit Carry Look ahead adder LIBRARY ieee; USE ieee.std_logic_1164.ALL;

entity CLA4 is port ( -- Inputs A, B : in std_logic_vector(3 downto 0); C_in : in std_logic; -- outputs S : buffer std_logic_vector(3 downto 0); C_out, PG, GG : buffer std_logic ); end CLA4;

architecture structure of CLA4 is component GPFullAdder port ( -- Inputs X, Y, Cin : in std_logic; -- Outputs G, P, Sum : buffer std_logic ); end component; component CLALogic port ( -- Inputs G, P : in std_logic_vector(3 downto 0); Ci : in std_logic; -- Outputs C: buffer std_logic_vector(3 downto 1); Co, PG, GG : buffer std_logic ); end component; signal G, P : std_logic_vector(3 downto 0); -- Carry internal signal signal C : std_logic_vector(3 downto 1);

begin CarryLogic: CLALogic port map (G, P, C_in, C, C_out, PG, GG); FA0 : GPFullAdder port map(A(0), B(0), C_in, G(0), P(0), S(0)); FA1 : GPFullAdder port map(A(1), B(1), C(1), G(1), P(1), S(1)); FA2 : GPFullAdder port map(A(2), B(2), C(2), G(2), P(2), S(2)); FA3 : GPFullAdder port map(A(3), B(3), C(3), G(3), P(3), S(3));

end structure; -- CLALogic

LIBRARY ieee; USE ieee.std_logic_1164.ALL;

entity CLALogic is port ( -- Inputs G, P : in std_logic_vector(3 downto 0); Ci : in std_logic; -- Outputs C: buffer std_logic_vector(3 downto 1); Co, PG, GG : buffer std_logic ); end CLALogic;

architecture Equations of CLALogic is signal GG_int, PG_int : std_logic; begin -- Concurrent assignment statements with delays C(1) <= G(0) or (P(0) and Ci) after 100 ns; C(2) <= G(1) or (P(1) and G(0)) or (P(1) and P(0) and Ci) after 100 ns; C(3) <= G(2) or (P(2) and G(1)) or (P(2) and P(1) and G(0)) or (P(2) and P(1) and P(0) and Ci) after 100 ns; PG_int <= P(3) and P(2) and P(1) and P(0) after 100 ns; GG_int <= G(3) or (P(3) and G(2) ) or (P(3) and P(2) and G(1)) or (P(3) and P(2) and P(1) and G(0)) after 100 ns;

Co <= GG_int or (PG_int and Ci); PG <= PG_int; GG <= GG_int; end Equations;

-- GPFullAdder

LIBRARY ieee; USE ieee.std_logic_1164.ALL;

entity GPFullAdder is port ( -- Inputs X, Y, Cin : in std_logic; -- Outputs G, P, Sum : buffer std_logic ); end GPFullAdder;

architecture Equations of GPFullAdder is signal P_int : std_logic; begin G <= X and Y; P <= P_int; P_int <= X xor Y; Sum <= P_int xor Cin; end Equations;

-- 16 bit Carry Look Ahead Adder

LIBRARY ieee; USE ieee.std_logic_1164.ALL;

entity CLA16 is port ( A, B : in std_logic_vector (15 downto 0); Ci : in std_logic; S : out std_logic_vector(15 downto 0); Co, PG, GG : out std_logic); end CLA16;

architecture Structure of CLA16 is component CLA4 port ( -- Inputs A, B : in std_logic_vector(3 downto 0); C_in : in std_logic; -- outputs S : buffer std_logic_vector(3 downto 0); C_out, PG, GG : buffer std_logic );

end component; component GPFullAdder port ( -- Inputs X, Y, Cin : in std_logic; -- Outputs G, P, Sum : buffer std_logic ); end component; component CLALogic port ( -- Inputs G, P : in std_logic_vector(3 downto 0); Ci : in std_logic; -- Outputs C: buffer std_logic_vector(3 downto 1); Co, PG, GG : buffer std_logic ); end component; signal S0, S1, S2, S3, G, P : std_logic_vector(3 downto 0); signal C: std_logic_vector(3 downto 1); alias A0: std_logic_vector(3 downto 0) is A(3 downto 0); alias A1: std_logic_vector(3 downto 0) is A(7 downto 4); alias A2: std_logic_vector(3 downto 0) is A(11 downto 8); alias A3: std_logic_vector(3 downto 0) is A(15 downto 12); alias B0: std_logic_vector(3 downto 0) is B(3 downto 0); alias B1: std_logic_vector(3 downto 0) is B(7 downto 4); alias B2: std_logic_vector(3 downto 0) is B(11 downto 8); alias B3: std_logic_vector(3 downto 0) is B(15 downto 12); begin CarryLogic: CLALogic port map(G, P, Ci, C, Co, PG, GG); CLAa : CLA4 port map (A0, B0, Ci, S0, open, P(0), G(0)); CLAb : CLA4 port map (A1, B1, C(1), S1, open, P(1), G(1)); CLAc : CLA4 port map (A2, B2, C(2), S2, open, P(2), G(2)); CLAd : CLA4 port map (A3, B3, C(3), S3, open, P(3), G(3)); S <= S3 & S2 & S1 &S0; end Structure;

Hierarchical