i)

ii)

iii)

iv)

This question is about the Verilog code below. endmodule module swap2(a,b); input [1:0] a; output [1:0] b; assignb[1]=a[0];assignb[0]=a[1]; endmodule Which bit of the output bus d is connected to c[0] ? Which bit of the output bus d is connected to c[1] ? Which bit of the output bus d is connected to c[2] ? Which bit of the output bus d is connected to c[3]