I need a cache emulator and I am relying on my experts to put together a solution in Verilog. Much like assignments you will have in your career, the input and outputs are known but the challenge is figuring out how to get there. The cache emulator should look like the 8-block cache described in chapter 5 of your book on page 386-389.

The 8-block cache will have:

1. Index of 3 bits
2. 1 bit Valid indicator
3. Tag of 2 bits
4. Data size will be a word (4 bytes)
5. The cache should be initially zero

The memory should be:

1. Word size (4 bytes)
2. initialized with values starting at 0 and incrementing by 1 at each address.
3. Size should be the number of addressable values by cache

Program Operation:

1. Input should be the list of values specified from the book (and copied below).
2. Output should be:
   1. Hit/miss along with the data at the memory location specified that is loaded into the block
   2. Final output of the entire cache contents.

Decimal address of reference 22 26 22 26 16 3 16 18 CO 16 Binary address of reference 10110, 11010, 10110. 11010, 10000 00011 10000 10010, 10000 two two two two two two two two two Hit or miss in cache miss (5.6b) miss (5.6c) hit hit miss (5.6d) miss (5.6e) hit miss (5.6f) hit Assigned cache block (where found or placed) (10110, mod 8) = 110, two two (11010 two mod 8) = 010, (10110, mod 8) = 110, (11010. mod 8) = 010, two two two (10000 mod 8) = 000, (00011two mod 8) = 011, (10000 mod 8) = 000, (10010, mod 8) = 010, two (10000, mod 8) = 000, two two two two two two two two two two