i need a verilog code for the problem along with a testbench and simulated output waveform in modelsim

In class we discussed the design of PRBS generators and monitors. Using Verlog implement and simulate a PRBS generator and monitors per the diagram below. the diagram) sequence of random bits. Connect the monitor and generator and simulate them to show the monitor locks to the generators pattern as per beloa. b. [BONUS] Extend your generator and monitor design to produce an S-bit wide n = S in the diagram) sequence of random bits. and a screen shot of the wave Again submit the Vrilog traces showing correct operation of a. and optionally b. reset lock PRBS Generator PRBS Monitor bit error In class we discussed the design of PRBS generators and monitors. Using Verlog implement and simulate a PRBS generator and monitors per the diagram below. the diagram) sequence of random bits. Connect the monitor and generator and simulate them to show the monitor locks to the generators pattern as per beloa. b. [BONUS] Extend your generator and monitor design to produce an S-bit wide n = S in the diagram) sequence of random bits. and a screen shot of the wave Again submit the Vrilog traces showing correct operation of a. and optionally b. reset lock PRBS Generator PRBS Monitor bit error