I need answer for attached question You execute the following code segment exactly once on a machine with $32-$bit integer values.int a $[128][128],$ junka$[$OFFSET$],$c $[128][128]$;

int i$,$ j;

for $($i$=0$; i $<mn\; id="EditorElement\_2684267">1</mn><mn\; id="EditorElement\_2684268">2</mn><mn\; id="EditorElement\_2684269">8</mn>$; i$++)\{$ c$[$i$][$j$]=(2*$ b$[$i$][$j$])+(3*\backslash$textrm$\{$a$\}[\backslash$textrm$\{$i$\}][\backslash$textrm$\{$j$\}])$;$\}\}$The machine configuration is:

$32-$bit integer; $32-$bit words; byte addressed on word boundaries.

L$1$ data cache: $8KB,16-$byte block size, direct mapped, no write$-$allocate, write$-$through. Hit time for

$L1=1$ clock.

L$2$: $256KB,16$ byte block size, direct mapped, write allocate, write$-$back, hit time for L$2=1$ clock to

process $L1$ miss $+3$ clocks to access $L2=4$ clocks. Memory access time $($after $4$ clocks to discover

that there is an L$2$ miss$)=50$ clocks.

Assume:

Array a $[]$ starts at address $0x00000000$ and arrays are allocated contiguously. The assembly code

always fetches $b$ before $a$ on a given iteration.

Physical addresses for data map identically to their virtual addresses.

Machine starts with invalidated caches.

Writing all modified data from the L$2$ cache to main memory is done after the code runs and is

included in all answers to the questions.

Only data cache behavior is considered $($ignore instruction fetching$).$ Caches are blocking with no

pre$-$fetching of data.

a$)$ How many clocks are spent to handle L$2$ misses $($i$.$e$.$ give the number of clocks waiting for main

memory beyond whatever clocks would have been required to access $L2$ cache if there had been hits$).$

Justify your answer.

b$)$ How many clocks are spent to handle L$1$ misses that are hit in L$2.$ Justify your answer.

Hint: Layout the arrays in the cache and see how many times they wrap around and see what is the

effect of junka and junkb on the layout of the arrays.