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I need help with shift-add-3 module for boolean part. tq in advance 3. Overall Design For this lab you are required to design the following

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I need help with shift-add-3 module for boolean part. tq in advance

3. Overall Design For this lab you are required to design the following system: Binary BCD + 3x4 Binary to BCD BCD to 7- 7-seg + 3x7 9 segment PRELAB Use any internet resources that you can Google to construct the following: 1. Truth table of shift-add-3 module. 2. The shift-add-3 modules schematic connection to convert 9-bit binary into 3 decimal digits. 3. Schematic diagram of common anode and common cathode 7 segment circuit connection. SIMULATION WORKS AND EXERCISES 1. Shift-Add-3 Module Each group are required to write the Verilog code of the shift-add-3 module either as: 1. Boolean 2. Behavioural by if-else, or, 3. Behavioural by case statement. Refer to the table at the end of this document to see which mode is assigned to your group. Suggested module declaration: module ShiftAdd3 (input 13:0] theBin, output [3:0] theAdd3); Declare ports as reg if necessary. 3. Overall Design For this lab you are required to design the following system: Binary BCD + 3x4 Binary to BCD BCD to 7- 7-seg + 3x7 9 segment PRELAB Use any internet resources that you can Google to construct the following: 1. Truth table of shift-add-3 module. 2. The shift-add-3 modules schematic connection to convert 9-bit binary into 3 decimal digits. 3. Schematic diagram of common anode and common cathode 7 segment circuit connection. SIMULATION WORKS AND EXERCISES 1. Shift-Add-3 Module Each group are required to write the Verilog code of the shift-add-3 module either as: 1. Boolean 2. Behavioural by if-else, or, 3. Behavioural by case statement. Refer to the table at the end of this document to see which mode is assigned to your group. Suggested module declaration: module ShiftAdd3 (input 13:0] theBin, output [3:0] theAdd3); Declare ports as reg if necessary

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