I need the following in verilog. I have also attached the test bench.

CODE

// Netflix has been engaged by movie studios to advertise new movies. // Netflix will show visitors one of 4 ads based on the kind of movie // they last watched.

// The following characteristics of the last watched movie are // considered: // - Whether the movie was animated? (A = 1 means the movie was // animated; otherwise A = 0) // - Whether the starring actor was female (F = 1) or male (F = 0)? // - The type of movie: (T = 2'b00 (action movie), 2'b01 (romance), // 2'b10 (comedy), 2'b11 (thriller))

// The ad served is chosen by the following rules: // - "A Good Day to Die Hard" (M = 2'b00) will be shown to viewers of // action movies and thrillers, unless they are animated or had a // female starring actor. // - "Safe Haven" (M = 2'b01) will be selected for people who had // viewed romance movies or movies with a female starring actor that // are not comedies. // - When the previous two movie ads aren't shown, "Escape from Planet // Earth" (M = 2'b10) will be shown to people viewing animated movies, // comedies, or action movies. // - Otherwise, "Saving Lincoln" (M = 2'b11) will be shown.

module movies(M, A, F, T); output [1:0] M; input A, F; input [1:0] T;

endmodule // movies

TEST BENCH

module test;

// these are inputs to "circuit under test" reg A; reg F; reg [1:0] T; // wires for the outputs of "circuit under test" wire [1:0] M; // the circuit under test movies m(M, A, F, T); initial begin // initial = run at beginning of simulation // begin/end = associate block with initial $dumpfile("test.vcd"); // name of dump file to create $dumpvars(0, test); // record all signals of module "test" and sub-modules // remember to change "test" to the correct // module name when writing your own test benches // test all input combinations A = 0; F = 0; T = 0; #10; A = 0; F = 0; T = 1; #10; A = 0; F = 0; T = 2; #10; A = 0; F = 0; T = 3; #10; A = 0; F = 1; T = 0; #10; A = 0; F = 1; T = 1; #10; A = 0; F = 1; T = 2; #10; A = 0; F = 1; T = 3; #10; A = 1; F = 0; T = 0; #10; A = 1; F = 0; T = 1; #10; A = 1; F = 0; T = 2; #10; A = 1; F = 0; T = 3; #10; A = 1; F = 1; T = 0; #10; A = 1; F = 1; T = 1; #10; A = 1; F = 1; T = 2; #10; A = 1; F = 1; T = 3; #10; $finish; // end the simulation end initial begin $display("inputs = A, F, T outputs = M"); $monitor("inputs = %b %b %b outputs = %b time = %2t", A, F, T, M, $time); end endmodule // test