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I need to creat a vhdl code that can solve my design problem with my state diagram and be used in conjuction with logism evolution

I need to creat a vhdl code that can solve my design problem with my state diagram and be used in conjuction with logism evolution for this state diagram.
My criteria: At startup, we initially focus on identifying the sequence 000 followed by another non-overlapping occurrence of 000.
Once we've detected the leading sequence (000) twice, not necessarily in immediate succession, we cease further recognition of subsequent instances of 000 and instead aim to identify the sequence 111 once.
Upon detecting the sequence 111 once, we then disregard any subsequent instances of 111 and resume our search for the sequence 000, aiming to detect it twice again. This cycle persists, alternating between identifying the 000 sequence twice and the 111 sequence once.
note: Please thoroughly document the code
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