I only need $($a$)$ answered. Exercise $7\mathrm{.}14$ Repeat Exercise $7\mathrm{.}13$ for the following MIPS instructions $($a$)$ bne $($b$)1$b $($c$)1$bu $($d$)$ andiExercise $7\mathrm{.}13$ Modify the multicycle MIPS processor to implement one of the following instructions. See Appendix B for a definition of the instructions. Mark up a copy of Figure $7\mathrm{.}27$ to indicate the changes to the datapath. Name any new Exercises control signals. Mark up a copy of Figure $7\mathrm{.}39$ to show the changes to the controller FSM$.$ Describe any other changes that are required.PCWrite PCEn lorD Control PCSrc MemWrite Unit ALUContral IRWrite Op rite WE WE$3$ Zero RD$1$ RD$2$ A$1$ RD ALUResuit A$2$ Instr$/$Data Register A$3$ File Data Signlmm Sign Extend Figure $7\mathrm{.}27$ Complete multicycle MIPS processorS$0$: Fetch S$1$: Decode Reset$/$ Alu AluSrcA$0$ ALUSrcA $=0$ ALUScB $=11$ ALUOp $00$ ALUSrcB $01$ ALUOp $00$ IRWnite PCWrite Op R$-$type S$6$: Execute S$8$: Branch ALUSrcA $=1$ ALUSrcB $=00$ ALUOp $01$ PCSrc$=1$ Branch ALUSrcA $=1$ ALUSrcB $10$ ALUOp $=00$ ALUSrcA $=1$ ALUSrcB $=00$ ALUOp $10$ Figure $7\mathrm{.}39$ Complete multicycle control FSM S$7$: ALU Writeback S$5$: MemWrite S$3$: MemRead lorD$=1$ MemWrite RegDst$1$ RegWrite lorD$=1$ S$4$: Mem Writeback RegDst $=0$ RegWnite