I really dont understand this. Can someone draw it please?

For the following three questions, you will be designing a memory subsystem for a computer with an $8-$bit data bus and a $16$bit address bus. The memory subsystem consists of a combination of ROM and RAM, implemented either as individual memory chips or as arrays of memory chips, with each type of memory occupying a portion of the available $64K$ addres space. Your partial address decoding logic must ensure that these chips are active only within the range of addresses described below.

I. $(10$ points$)$ The first memory device in this system is an $8K$ firmware ROM corresponding to the memory address range $$0000$ to $$1FFF.$ Show the logic to generate a CE signal$($s$)$ for this ROM, which should be active low, if one $8K$ x $8$ ROM chip is used. Draw and test the complete circuit in Logisim within the $"$Q$1"$ subcircuit in the provided file, using traditional logic gates.

$($Hint: Note that an $8K$ x $8$ memory chip has a capacity of $8192$ bytes; since only one of these chip is needed to create a single $8Kx8$ ROM memory unit, only one CE signal is needed for this chip.$)$

Logisim Q$1$ Below What do I do$?$

II$.(10$ points$)$ Next, add a $16K$ program ROM unit corresponding to the memory address range $$C000$ to $$FFFF.$ Show the logic to generate the CE signal$($s$)$ for this ROM, which should be active low, if two $8K8$ ROM chips are used. Draw and test the complete circuit in Logisim within the $"$Q$2"$ subcircuit in the provided file, using traditional logic gates.

$($Hint: Again, an $8$ K $88$ memory chip has a capacity of $8192$ bytes, so you will need to use an array of two of these chips to create a single $16K$ x $8$ memory unit, which has a total capacity of $16384$ bytes. The chip$-$enable signal $!$CEO should be active in the lower half of this address range, and the chip$-$enable signal $!$CE$1$ should be active in the upper half of this address range.$)$

Logisim Q$2.$ What do I do$?$

A$11$

A$12$

A$13$

OICEO

A$14$

O$)$CE$1$

A$15$

III. $(10$ points$)$ Next, add a $16$K RAM unit corresponding to the memory address range $$4000$ to $$7FFF.$ Show the logic to generate the CE signal$($s$)$ for this RAM, which should be active low, if $2K8$ RAM chips are used. Draw and test the complete circuit in Logisim within the $"$Q$3"$ subcircuit in the provided file.

$($Hint: Note that a $2K8$ RAM chip has a capacity of $2048$ bytes, so you will need to use an array of eight of these chips to create a single $16K8$ memory unit. Instead of using traditional logic gates to generate separate CE signals for all eight chips, I suggest that you use a $3$:$8$ decoder in your design. The chip$-$enable signal $!$CEO should correspond to the chip at the bottom of this addres range, and the chip$-$enable signal $!$CE$7$ should correspond to the chip at the top of this address range. When adding the decoder in Logisim, be sure to set the "Three$-$State" property to $"$No$,"$ and the "Disabled Output" property to "Zero," so that the outputs function a sexpected when the e entire RAM unit is disabled. The "Enable" input of the decoder should be used to disable all outputs when the active address is outside the specifed range; since Logisis's decoder outputs are active$-$high, you may need to use NOT gates to change the outputs to active$-$ow$,$

Again, I highly recommend that you use command$-$line verification to test your completed work. The "testing harness provided with this file will automatically count through a range of $16-$bit memory addresses in $2K$ increments, one on each row, starting at address $$0000$; if any memory chip is active at the current address, the corresponding CE signal in that row should also be active. A correct implementation will output a $0$ if the $CE$ signal$($s$)$ are active and a $1$ if the signal$($s$)$ are inactive. Since only one memory chip should be active on the bus at any one time, any single row of the output should contain at most only one $0$

When your work is complete, your results$-$displayed at the console in table format, as described in the Logisim tutorial$-$should match the following:

Main Board. Should not be changed: