I want a system verilog code for this Hamming code$(15,11).$Hamming codes are a set of codes used for error detection and correction that may occur during data transmission or even during data storage. This is achieved through the creation of parity bits. One of these codes is the $(15,11)$ code, which, as its name suggests, converts an $11-$bit word into a $15-$bit word by calculating $4$ parity bits.

An example of the calculation of the Hamming $(15,11)$ code is illustrated below. Given $11$ input bits, the Hamming code generates $4$ parity bits, which in combination with the input form the output as shown in Figure $1.$ The calculation of the parity bits for the Hamming $(15,11)$ code is detailed in the figure. The first parity bit $($P$1)$ is calculated using the XOR of the bits located at positions $3,5,7,9,11,13,$ and $15$ of the output word. These bits correspond to bits $1,2,4,5,7,9,$ and $11$ of the input. The remaining parity bits are calculated in the same way.

The circuit is in an initialization state as long as the rst signal is at the logical value $\text{'}1\text{'}.$ When the value of rst drops to logical $\text{'}0\text{'},$ the circuit starts directly and reads the $11$ input bits serially. Each time an input bit is read from the inp signal, it is stored in the input buffer. The storage of inputs in the input buffer can be done either using a decoding$-$demultiplexing circuit with the help of a counter $($as shown in picture$)$ or by any other means $($e$.$g$.,$ shift register$).$

When all $11$ input bits are stored in the input buffer, the circuit should calculate the $4$ parity bits. Subsequently, the $11$ input bits and the $4$ parity bits should be stored in the output buffer before being sent to the output.

When the output buffer contains all $15$ output bits, the circuit starts sending the bits serially to the out output. Initially, the $11$ input bits will appear at the output, followed by the $4$ parity bits. As with reading the inputs, you can choose any method for the serial transmission of the outputs.

ATTENTION! Both during input reading and output transmission, data is transmitted in consecutive cycles. This means that with the drop of rst$,$ the circuit reads the input for $11$ consecutive cycles. Similarly, when the output buffer contains all the necessary data, the $15$ output bits should be transmitted in $15$ consecutive cycles.

Once the circuit finishes sending the data, it should wait for its initialization by the rst signal to restart its operation. Below is an example of the circuit's operation, taking as input the word $.$ The code must be like this module hamming$\_$core $($ input logic clk$,$ input logic rst$,$ input logic inp,

input logic out

$)$;

$//$your code here

endmodule