I want a verilog code to design the hardware to implement the following function:

$E=\frac{A}{2^i}+B{2}^j$

$F=EC$

Where:

A$,$ B$,$ C and E are $8-$bit unsigned numbers

i and $j$ are $3-$bit unsigned numbers.

$F$ is $16-$bit unsigned number

Design Specification:

Implement the design using Verilog language. Do not use the following math operations:

$,,-+\frac{,}{?},$ shift$/$rotate$.$ You need to implement them yourself.

The top design name is mydesign and the port definition is illustrated below. You must

use the below testbench and template in your design.

Use your own choice of multiplier algorithm to implement the multiplier.