i want answer in 15 minutes

10 points 2. For the given sequence of instructions, fill the table below with the pipeline stages for each instruction. IMPORTANT: Assume that each load instruction causes 2 automatic stalls after the memory cycle. BUT assume "forwarding, that is the result of an ALU execution is available to the input of the execution stage in the beginning of the next elock cycle. If possible try to reduce the number of eycles by changing the sequence of the code without altering the output. How many cycles does it take to execute his piece of code? 25 peints \begin{tabular}{|c|c|c|} \hline \multicolumn{2}{|c|}{ alwa AAba } & \multirow[b]{2}{*}{ nux oflim (Dwa frimi) } \\ \hline Ter & & \\ \hline \end{tabular} \begin{tabular}{|c|c|c|} \hline \multicolumn{2}{|c|}{ mat Alber } & \multirow[b]{2}{*}{ Ble 6 Cofler inuis sitery } \\ \hlinem4 & & \\ \hline & & \\ \hline & & \\ \hline \end{tabular} 25 points 7. In a cache system we have the following attributes: 256MB of physical memory space 4MB of cache 256KB per cache line a) Determine number of lines in cache. b) Determine the number of address bits out of the processor. c) Determine the number of bits needed for the block offset section of the address. d) If our cache is 4-way set associative, how many sets are there in the cache? e) How many bits are needed to select sets in this cache? f) Determine the number of bits of the tag, if 8-way set associative cache is implemented. g) Fill the table below with proper number of bits in each portion of the address bit map: h) Assume the CPU has put the following address on the address bus: [A B C D E F 7] Clearly list the bits and identify the meaning of each segment of the address based on your answer to part c. Assume cache lines 0 to 2 in this particular set are used by other memory blocks, what is the definite cache line number to be used for this memory access