I want to know the blank ( Serial - subtractor circuit ). Would you please help me?

Objectives ? Understand Verilog language and use basic grammar. Use a Verilog language to construct a digital circuit. ? Use a Quartus Prime / Modelsim to simulate digital circuit. Understand the basic digital design flow through the serial adder / subtractor design. Data and Observations Part I: Circuit Design Serial-adder Serial-subtractor surm-out Shift register Full Adder Shift register Shift register ca sum clock reset resetn start Control FSM Fig. 12-24. Block diagram of serial-adder / serial-subtractor circuit. Objectives ? Understand Verilog language and use basic grammar. Use a Verilog language to construct a digital circuit. ? Use a Quartus Prime / Modelsim to simulate digital circuit. Understand the basic digital design flow through the serial adder / subtractor design. Data and Observations Part I: Circuit Design Serial-adder Serial-subtractor surm-out Shift register Full Adder Shift register Shift register ca sum clock reset resetn start Control FSM Fig. 12-24. Block diagram of serial-adder / serial-subtractor circuit