i was givn this which i am happy with. can you help me with Designinga circuit to implement your state machine. Show the minimisation process and the final equations in your report.

Implement and simulate your design using Digital$/$Logisim to verify functionality

design a finite state machine $($FSM$)$ to detect the sequence $00100$ in a bit stream. The output should be a single bit that goes high $(1)$ whenever the sequence has been detected. Note that the input $00100100$ should result in two detections.Note however, that it does not consider overlapping sequences. make sure you use the minimum states you can. this is i have done, can you do it in $4$ states?o design a finite state machine $($FSM$)$ that detects the sequence $00100$ in a bit stream using a minimal number of states, we can indeed accomplish this with just $4$ states. Here is the state diagram and description for such an FSM:

States and Transitions:

State S$0$: Initial state, waiting for the first $0.$

Transition to S$1$ on $0.$

Remain in S$0$ on $1.$

State S$1$: Detected the first $0.$

Transition to S$2$ on $0.$

Return to S$0$ on $1.$

State S$2$: Detected $00.$

Transition to S$3$ on $1.$

Stay in S$2$ on $0.$

State S$3$: Detected $001.$

Transition to S$4$ on $0.$

Return to S$0$ on $1.$

State S$4$: Detected $0010.$

Transition to S$0$ on $0$ and output $1($detection complete$).$

Return to S$0$ on $1.$